1. Field
This disclosure relates generally to semiconductors, and more specifically, to semiconductor memories and the manufacture thereof.
2. Related Art
Split gate memory cells have found a particular use in non-volatile memories (NVMs) that have many applications. A split gate memory cell has two distinguishable channel regions, respectively controlled by a select gate and a control gate, which are electrically separated by a dielectric. The select gate channel acts as an access device to select the memory cell under the control gate during read or program operations. A particular concern in any memory device is to have a sufficient voltage differential between program and erase states. This voltage differential may be considered as a memory window for differentiating between program and erase modes. Efficient removal of electrons from the storage element(s) during an erase operation helps to increase the size of the memory window and therefore improve program and erase efficiency. In some split-gate memory structures a charge storage layer is used having nanoclusters which hold charge. It may be difficult to remove all electrons from some portions of a nanocluster layer. For example, complete removal of charge from the nanoclusters which lie in the dielectric between the select gate and the control gate or at a corner of the control gate that is closer to the select gate, may be difficult. Any residual charge left in a nanocluster layer that is close to a channel of a memory cell can result in a partially erased memory cell. Such partially erased memory cells result in variation in the threshold voltage distribution of the memory in the erased state.